1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to a method of forming a semiconductor package with flip chip interconnect and lead-free bumps.
2. Related Art
Recent packaging development work on semiconductor die with ultra-low K (ULK) dielectrics and lead-free bumps has shown a consistent issue with inter-layer dielectric delamination under the C4 flip-chip solder bump or interconnect. The C4 bumps are also referred to as electrical contacts. This delamination is known as white bumps or ghost bumps due to its appearance under acoustic microscopy analysis, and occurs more prevalently on large die/large packages. Mechanical modeling and recent experience has shown that the outer rows of bumps have the highest probability of experiencing delamination under the bump as these locations experience the highest stress during chip attach reflow cool down.